Voltage regulation circuits have many applications in power supply systems to provide a regulated voltage at a predetermined multiple of a reference voltage. In low drop-out regulator designs, there commonly occur two poles at lower frequencies, one due to the output impedance of the circuit's power MOS transistor together with load capacitor and another due to the gate capacitance of the power MOS with impedance connected to this node. These two poles come very close to each other in many designs. One way to separate these poles is to increase the value of a load capacitor, so as to move the load pole towards the lower frequencies. However, this increases the cost of this capacitor and it needs the board area. In many applications, this needed increase in board area can be very difficult to come by. It also results in reduction of loop bandwidth and, hence, reduction in response time. Another way to separate these poles is to increase the current the regulator's buffer stage, to thereby reduce the impedance in that arm of the circuit and move the power MOS pole towards the higher frequencies. Although this again helps to separate the poles, it is done at the cost of increased quiescent current of the LDO for all loads. As both of these approaches have drawbacks, there is consequently room for improvement in the design of low drop out regulation circuits.